Avionics computer systems designed for use at high altitudes are especially vulnerable to single-event upsets caused by the collision of cosmic rays, or atmospheric particles (e.g., protons, neutrons) liberated by cosmic rays, with aircraft microelectronics. While the resulting state change, e.g., flipping a bit to its complement, may be a “soft error” not permanently damaging to the hardware, the built-in hardware correction logic may have no practical way of correcting such an error, especially if a double-bit error occurs (i.e., two bits in the same “word” are flipped to their respective complements). Resetting the module may not be an acceptable solution for a safety-critical multi-core avionics processing system. Prior approaches to this problem, such as simultaneous access to RAM or newer processor privilege modes, may not provide optimal solutions in a newer multi-core processing environment.
It may therefore be desirable to prevent a module reset due to a double-bit RAM error caused by single-event upsets (ex.—bit errors) by providing a means of correcting single-bit errors in the multi-core processing resource (MCPR). It may further be desirable to provide a means of correcting single-bit errors in the MCPR that prevents memory mapped to an executing partition (ex.—core) of the processor system from being modified by another processor or core (or by the hypervisor of the processor system) during testing. It may further be desirable to provide a means of correcting single-bit errors in the MCPR that accounts for single-point ownership and access to error detection and correction (EDAC) registers of a system-on-chip (SoC) module of the processor system. It may further be desirable to provide a means of correcting single-bit errors in the MCPR that is not only scalable (e.g., of selectable size or range) but capable of testing the entirety of system RAM, not just that portion of system RAM mapped by the hypervisor.